This invention is in the field of bipolar and field effect transistor devices, and relates more particularly to improved combined bipolar-field effect transistor RESURF devices.
The general concept of combining bipolar and field effect transistors in a single device is well-known in the art. For example, combined bipolar-junction field effect transistor devices are shown in U.S. Pat. No. 4,095,252 and IBM Technical Disclosure Bulletin, Vol. 19, No. 11, April 1977. Additionally, a combined vertical bipolar-DMOS device is shown in U.S. Pat. No. 4,344,081. Generally speaking, when such devices are used for high-power switching applications, a bipolar transistor and a field effect transistor are combined in order to achieve a single integrated device which features both the faster switching response of the field effect transistor and the lower on-resistance of the bipolar transistor.
In order to achieve a higher level of performance in such devices, an ongoing effort has been made to improve the breakdown and switching characteristics of the devices. For example, it has been found that the breakdown characteristics of high-voltage semiconductor devices generally can be improved by using the REduced SURface Field (or RESURF) technique, as described in "High Voltage Thin Layer Devices (RESURF Devices)", "International Electron Devices Meeting Technical Digest", December, 1979, pages 238-240, by Appels et al, and U.S. Pat. No. 4,292,642, incorporated herein by reference. Essentially, the improved breakdown characteristics of RESURF devices are achieved by employing thinner but more highly doped epitaxial surface layers to reduce surface fields.
The RESURF technique was applied to lateral double-diffused MOS transistors, as reported in "Lateral DMOS Power Transistor Design", "IEEE Electron Device Letters", Vol. EDL-1, pages 51-53, April, 1980, by Colak et al, and the result was a substantial improvement in device characteristics. In high-voltage DMOS devices, there is normally a trade-off between breakdown voltage and on-resistance, with the goal being to increase the breakdown voltage level while maintaining a relatively low on-resistance. Using the RESURF technique, and for reference assuming a constant breakdown voltage, an improvement (e.g. decrease) in on-resistance by a factor of about 3 may be obtained in a device occupying the same area as a conventional (thick epitaxial layer) DMOS device. An additional technique for improving the operating characteristics of DMOS transistors by using buried and surface field shaping layers is shown in U.S. Pat. No. 4,300,150.
Nevertheless, a further improvement in the on-resistance and switching characteristics of such devices would be extremely desirable, particularly for high-voltage power switching devices where such characteristics are of considerable importance. Additionally, for combined bipolar-field effect transistor devices using the RESURF principle, it would be desirable to improve the manufacturing yield and minimize the area occupied by the device for a given set of switching, high-voltage, and on-resistance characteristics.
Such a combined device is described in a U.S. patent application entitled COMBINED BIPOLAR-FIELD EFFECT TRANSISTOR RESURF DEVICES, by Jayaraman, Singer and Stupp, filed concurrently herewith and incorporated herein by reference. However, it has been found that such combined bipolar-field effect transistor devices still may suffer from certain drawbacks, such as requiring a substantial amount of base drive current for a desired level of on-resistance and a commensurately large base drive power source, and having a significant unwanted internal power dissipation. Additionally it would be desirable to improve the isolation of the combined transistor from other devices in the same substrate, and to provide faste operation.